Prof. Dr.-Ing. Christof Paar
- Chair - Chair Embedded Security
- Leitung - Horst Görtz Institute for IT-Security Max Planck Institute for Cybersecurity and Privacy
Prof. Dr.-Ing. Christof Paar
Max Planck Institute for Cybersecurity and Privacy
- (+49)(0)234 / 32 - 22994
- firstname.lastname@example.org PGP key
- 1988 B.Sc. in Communication Engineering, University of Applied Sciences Cologne
- 1991 M.Sc. in Electrical Engineering, Universität Siegen
- 1994 Ph.D. thesis "Computer Architectures for Galois Field Arithmetic", Institute for Experimental Mathematics, University of Essen
- 1995-2001 Assistant and associate professor, ECE Department, Worcester Polytechnic Institute, Massachusetts, USA
- 1999 Co-founder of CHES, the Conference on Cryptographic Hardware and Embedded Systems
- 2001-19 Chair for Embedded Security, ECE Department, Ruhr-Universität Bochum
- 2004 Co-founder of ESCRYPT GmbH - Embedded Security (now part of Bosch)
- 2004-07, 2010-12, 2016-17 Director of the Horst Görtz Institute for IT-Security
- 2008- Affiliated Professor, ECE Department, University of Massachusetts Amherst
- 2012-2017 Spokesperson for the doctoral school "Cryptography in Ubiquitous Computing"
- 2016 Spokesperson for the doctoral school "Brave New World: Security for Humans in Cyberspace (SecHuman)"
- 2019 Co-Spokesperson of the Cluster of Excellence "CASA - Cyber Security in the Age of Large-Scale Adversaries" (with Th. Holz und E. Kiltz)
- 2019- Founding director of the Max Planck Institute for Cybersecurity and Privacy
- Curriculum Vitae
- Portrait for download
- 2017: IACR Fellow (International Association for Cryptologic Research)
- 2016: ERC Advanced Grant for research in hardware security (2.5m €)
- 2016: “Pwnie Award for Best Cryptographic Attack”, Black Hat Conference
- 2013: DHL Innovation Award
- 2012: Innovationspreis NRW (100k €)
- 2012: Best Paper Award, IEEE Symposium on Security & Privacy
- 2011: IEEE Fellow
- 2010: German IT Security Award (100k €)
- 2006: RUBITEC Technology Transfer Award for ESCRYPT GmbH
- 1998: NSF CAREER Award
- 1990: Friedrich-Ebert Foundation Fellowship
- Fast software algorithms for cryptographic implementations
- Hardware architectures for cryptography
- Physical attacks against real-world systems
- Cryptanalytical hardware
- Security in embedded applications such as smart cards, cars, etc.
- Security in mobile and ad-hoc networks
- "Cyber and Hardware Security in the Age of Large‐Scale Adversaries", invited talk at the Harvard Kennedy School, June 7, 2019
- "Why We Should Be Worried about Hardware Trojans", invited talk at The Summer Research Institute, EPFL, June 18, 2018.
- "Constructive and Destructive Aspects of Embedded Security for the Internet of Things", invited tutorial at CCS 2013 (ACM Conference on Computer and Communications Security), November 5, 2013.
- "Physical Attacks in a Physical World" , Invited Talk at the Massachusetts Institute of Technology, June 4, 2010.
- "The Next 10 Years of IT Security:RFID, BMWs and Burglars", Invited talk at Stanford University, August 20, 2008.
- "Light-Weight Cryptography for Ubiquitous Computing", Invited talk at the University of California, Los Angeles (UCLA), Institute for Pure and Applied Mathematics, December 4, 2006.
- "Breaking Ciphers with COPACOBANA - A Cost-Optimized Parallel Code-Breaker", Talk at the Workshop on Cryptographic Hardware and Embedded Systems - CHES 2006, Yokohama, Japan, October 11-1 2006.
- 143020: Bachelor Seminar Embedded Security
- 142025: Bachelor Practical Wireless Physical Layer Security
- 141022: Introduction to Cryptography I
- 141023: Introduction to Cryptography 2
- 142031: Introduction to Hardware Reverse Engineering
- 142032: Practical Research Project Embedded Security 1
- 142033: Practical Research Project Embedded Security 2
- 141024: Implementation of Cryptographic Schemes
- 147512: Colloquium: Embedded Security
- 142026: Master Practical Wireless Physical Layer Security
- 142024: Master Project Embedded Security
- 143021: Master Seminar Embedded Security
Towards Cognitive Obfuscation - Impeding Hardware Reverse Engineering Based on Psychological Insights
HAL—The Missing Piece of the Puzzle for Hardware Reverse Engineering, Trojan Detection and Insertion
Common-path depth-filtered digital holography for high resolution imaging of buried semiconductor structures
A Hardware-based Countermeasure to Reduce Side-Channel Leakage - Design, Implementation, and Evaluation
Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs
Preventing Scaling of Successful Attacks: A Cross-Layer Security Architecture for Resource-Constrained Platforms
Proof-of-Concept: Using Homomorphic Cryptography to Provide for Privacy in Modern Vehicular Environments
Fuming Acid and Cryptanalysis: Handy Tools for Overcoming a Digital Locking and Access Control System
Rights Management with NFC Smartphones and Electronic ID Cards: A Proof of Concept for Modern Car Sharing
Side-Channel Attacks on the Bitstream Encryption Mechanism of Altera Stratix II - Facilitating Black-Box Analysis using Software Reverse-Engineering
Privacy Preserving Payments on Computational RFID Devices with Application in Intelligent Transportation Systems
Experimentally Verifying a Complex Algebraic Attack on the Grain-128 Cipher Using Dedicated Reconfigurable Hardware
Wireless security threats: Eavesdropping and detecting of active RFIDs and remote controls in the wild
On the Vulnerability of FPGA Bitstream Encryption against Power Analysis Attacks – Extracting Keys from Xilinx Virtex-II FPGAs
"Modular Integer Arithmetic for Public Key Cryptography". I. Verbauwhede ed. in "Secure Integrated Circuits and Systems"
Three Years of Evolution: Cryptanalysis with COPACOBANA Special-purpose Hardware for Attacking Cryptographic Systems 2009
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology
On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoq Code Hopping Scheme
Security Requirements Engineering in the Automotive Domain: On Specification Procedures and Implementational Aspects
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies
Cantor versus Harley: Optimization and Analysis of Explicit Formulae for Hyperelliptic Curve Cryptosystem
DPA on n-bit sized Boolean and Arithmetic Operations and its Application to IDEA, RC6 and the HMAC-Construction
Efficient Implementation of Elliptic Curve Cryptosystems on the TI MSP430x33x Family of Microcontrollers
An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists
A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields