Side-Channel Attacks on the Bitstream Encryption Mechanism of Altera Stratix II - Facilitating Black-Box Analysis using Software Reverse-Engineering

Amir Moradi, David Oswald, Chris­tof Paar, Pawel Swierczynski

21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays- FPGA 2013, pages 91-100, February 11 - 13. ACM, 2013.


In order to protect FPGA designs against IP theft and related issues such as product cloning, all major FPGA manufacturers o er a mechanism to encrypt the bitstream used to con gure the FPGA. From a mathematical point of view, the employed encryption algorithms, e.g., AES or 3DES, are highly secure. However, recently it has been shown that the bitstream encryption feature of several FPGA product lines is susceptible to side-channel attacks that monitor the power consumption of the cryptographic module. In this paper, we present the rst successful attack on the bitstream encryption of the Altera Stratix II FPGA. To this end, we reverse-engineered the details of the proprietary and unpublished Stratix II bitstream encryption scheme from the Quartus II software. Using this knowledge, we demonstrate that the full 128-bit AES key of a Stratix II can be recovered by means of side-channel analysis with 30,000 measurements, which can be acquired in less than three hours. The complete bitstream of a Stratix II that is (seemingly) protected by the bitstream encryption feature can hence fall into the hands of a competitor or criminal - possibly implying system-wide damage if con dential information such as proprietary encryption schemes or keys programmed into the FPGA are extracted. In addition to lost IP, reprogramming the attacked FPGA with modi ed code, for instance, to secretly plant a hardware trojan, is a particularly dangerous scenario for many security-critical applications.

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