course: Introduction to Hardware Reverse Engineering

number:
142031
teaching methods:
lecture with integrated tutorials
media:
Moodle, computer based presentation, black board and chalk
responsible person:
Prof. Dr.-Ing. Chris­tof Paar
Lecturers:
Prof. Dr.-Ing. Chris­tof Paar (ETIT), M. Sc. Nils Albartus (ETIT), M. Sc. Steffen Becker (ETIT)
language:
german
HWS:
4
CP:
5
offered in:
summer term

dates in summer term

  • start: Thursday the 09.04.2020
  • lecture with integrated tutorials Thursdays: from 10:15 to 11.45 o'clock in ID 04/471
  • lecture with integrated tutorials Fridays: from 12:15 to 13.45 o'clock in ID 04/445

Exams

Form of exam:written
Registration for exam:FlexNow
Date:28.02.2020
Begin:12:30
Duration:120min
Room : ID 03/445
Form of exam:schriftlich + studienbegleitend
Registration for exam:FlexNow
Date:30.09.2020
Duration:120min

goals

The students are familiar with the fundamental aspects of complex logic circuit layout. This involves the comprehension of ASIC and FPGA architectures and their corresponding workflows, as well as the application of the associated tools and utilization of Hardware Description Languages (HDLs). Furthermore, the students have a profound theoretical understanding of the several steps required for the hardware reverse engineering process and know their implications. Last not least, students gather first practical experiences in gate-level netlist reverse engineering.

content

The so-called reverse engineering of devices plays an important role for legitimate users and hackers. On the one hand, reverse engineering can support companies and governments to discover IP (intellectual property) fraud or targeted manipulations. On the other hand, hackers utilize reverse engineering to steal and copy others' IP, or to implement backdoors into software or hardware circuits.

To get started with hardware reverse engineering successfully, it is important to understand the basic concepts of (forward) engineering integrated circuits. Therefore, the content of this lecture is structured into two parts:

Part I: Basic Principles of VLSI Design (VLSI stands for Very-large scale integration)

  • Introduction to ASIC and FPGA architectures
  • Introduction to combinatorial circuits
  • Sequential circuits
  • Hardware Description Languages (HDLs)
  • ASIC and FPGA workflows

Part II: Hardware Reverse Engineering

  • PCB analysis, delayering, imaging, and post-processing
  • FPGA bitstreasm reverse engineering
  • Gate-level netlist reverse engineering

recommended knowledge

Contents of the lecture "Informatik 3 - Digitaltechnik und Rechnerarchitektur"

miscellaneous

The examination of this class is spilt into a written Exam (60%) and projects (40%). 15% bonus points can be reached in addition.

In parallel to the lecture we will conduct a research project. The participation is voluntary and will be rewarded with 50€.